Liquid crystal displays (LCD) which have advantages of low radiation, compact in size and low energy consumption, are gradually replacing conventional cathode ray tube displays, therefore they are widely used in electronic products such as laptops, personal digital assistants (PDA), flat panel televisions or mobile phones, etc. Conventional liquid crystal displays employ external driver chips to drive the pixels on the panels to display images or pictures. In order to decrease the number of components used and to reduce manufacturing costs, in the recent years, it is gradually developed to have the structures of drive circuits integrated directly on the display panels; for example, the gate on array (GOA) technology is applied to integrate gate driver circuits on a liquid crystal panel.
Referring to FIG. 1, it shows a liquid crystal display device 100 of a prior art disclosed in Taiwan patent number 201044368 employing GOA technology. The liquid crystal display device 100 comprises a source driver circuit 110, a gate driver circuit 120, a timing controller 130, a plurality of data lines DL(1) to DL(M), a plurality of gate lines GL(1) to GL(N) and a pixel matrix. The pixel matrix includes a plurality of pixel units PX, each of the pixel units PX includes a thin film transistor switch TFT, a liquid crystal capacitor CLC and a storage capacitor CST respectively coupling with the corresponding data line and gate line, and a common voltage VCOM. The timing controller 130 produces signals required for operations of the source driver circuit 110 and the gate driver circuit 120, for examples, start pulse signals VST and frequency signals CK and XCK. The source driver circuit 110 produces corresponding data driven signals SD(1) to SD(M) for displaying images. The gate driver circuit 120 includes a plurality of shift registers SR(1) to SR(N) which are connected in series on different levels, their outputs OUT(1) to OUT(N) are correspondingly coupled with the gate lines GL(1) to GL(N), and can sequentially output gate drive signals SG(1) to SG(N) required by turning on of the thin film transistor switch TFT based on the frequency signals CK and XCK, and the start pulse signals VST. In order to provide sufficient driving capability, large-sized output thin film transistors are usually used for the shift registers SR(1) to SR(N).
Referring to FIG. 2, it shows a simplified block diagram of a liquid crystal display device 200 of a prior art disclosed in Taiwan patent number 201112211. FIG. 2 only shows a partial structure of the liquid crystal display device 200 which comprises a plurality of gate lines GL(1) to GL(N), a gate driver circuit 210 and a timing controller 220. The gate lines GL(1) to GL(N) are disposed in the display area 230 of the liquid crystal display device 200, and can correspondingly drive the pixels based on gate drive signals SG(1) to SG(N). The gate driver circuit 210 is disposed in the non-display area 240 of the liquid crystal display device 200, and includes a plurality of shift registers SR(1) to SR(N) disposed on different levels, and can output the gate drive signals SG(1) to SG(N) to the corresponding gate lines GL(1) to GL(N) based on start pulse signals VST(1), and frequency signals CK and XCK produced by the timing controller 220, and N is a positive round number. The liquid crystal display device 200 employs a structure which is arranged and driven on one end, in other words, the gate driver circuit 210 is disposed on the side of the gate lines GL(1) to GL(N), and the gate lines GL(1) to GL(N) are driven on the same side.
Referring to FIG. 3, it shows a timing diagram of the liquid crystal display device 200 of a prior art under operation. When the liquid crystal display device 200 is driven, the first level shift register SR(1) output the first level gate drive signal SG(1) based on the start pulse signal VST(1) produced by the timing controller 220, while the shift registers SR(2) to SR(N) on the second to the N level correspondingly output the gate drive signals SG(2) to SG(N) on the second to the N level, based on the start pulse signals VST(2) to VST(N) produced by the shift registers SR(1) to SR(N−1) on the previous levels. FIG. 3 shows a timing diagram of the start pulse signals VST(1) to VST(N) when the liquid crystal display device 200 shows two adjacent frames F(N) and F(N+1) amidst a few frames.
It is well known that the technology of gate on array (GOA) or gate in panel (GIP) for integrating gate driver circuits on a liquid crystal display device (TFT-LCD) panel can reduce the costs of integrated circuits, and the size of a board area around the panel; however, problems related to dependability, stability and power consumption of the complicated GOA circuits on the panel are headaches for designers. At least one shift register is required by a conventional GOA circuit to output one gate signal, therefore N shift registers are required for N gate lines for completing a loop circuit. External signal lines are also required to enter into more than N shift registers at the same time, thus problems with high power consumption and delay of signals will get more serious.
In order to reduce the RC distortion of the input signals and to enhance the dependability of the circuits, and provided that the circuits are driven properly, the GOA circuits needed to be simplified and the space occupied by the circuits needed to be reduced. Therefore it is necessary to provide a GOA circuit structure to tackle the aforementioned problems.